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Synthesis structure for counter

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mpatel

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Hi friends,

I was asked few questions in interview.

1. what is the difference between synthesis structure of 8 bit counter with signal and with variable?

2. How to design a circuit to detect a increment value (DO D1 D2 D3...) at rising_edge and falling_edge? mean at rising_edge Do, at falling edge D1 and so on...

3. Is it possible to detect falling edge in synthesis? If we use inverter, will it cause any problem in synthesis?

thanks
mukesh
 

Hi
There is no difference between synthesis of counter using signal and variable.
Only difference in simulation occurs.
 

As for the third question :

Yes detecting falling edge is possibe....

I have done so many times !!!!

I never faced a problem....

Even then
if our flip flops are +ve edge trigered


and we use inverter ..... it wil result in delay .....

and as such Setup time is increased .....

or say the circuit slows down

I dont understand ur 2nd question

Plz say it some other way

As for the first one ... it must be concerning VHDL

which I have just begun to study

Hope Someone will answer
 

Hi,
for third question, its posible to have negative edge triggered flop, why this question? was there some other catch in the question which i'm not able to get? if yes please let me know.
Also please elaborate 2nd question.
 

Thanks for the answers.

I describe 2nd question in other way.

I have an input values coming... (Do D1 D2 D3 D4 D5....).
Now I want to put this value on one signal (A) at both clock edge.
at rising_edge A = Do
falling_edge A = D1
rising_edge A = D2
falling_edge A = D3 and so on...

The 3rd question was related to this problem that how to detect falling edge. I insisted telling that in VHDL there is a command called
if falling_edge(clock)
but interviewer told there may be some problem of detecting falling edge in synthesis. I also never had any problem in synthesis. that means did he try to confuse with this false information?
 

The 3rd question was related to this problem that how to detect falling edge. I insisted telling that in VHDL there is a command called
if falling_edge(clock)
but interviewer told there may be some problem of detecting falling edge in synthesis. I also never had any problem in synthesis. that means did he try to
confuse with this false information?

No. the interviewer was right ! .. generally the synthesis tool requires that the clock signals are sampled at the "rising" edge and not falling edge.. this is because when the design goes to the layout level, the sampling at "negative" or "falling" edge adds an overhead to the timing and also area ..
 

mpatel said:
I describe 2nd question in other way.

I have an input values coming... (Do D1 D2 D3 D4 D5....).
Now I want to put this value on one signal (A) at both clock edge.
at rising_edge A = Do
falling_edge A = D1
rising_edge A = D2
falling_edge A = D3 and so on...
Click to expand...

you can simply use the keywords: rising_edge and falling_edge to detect that...for the if statement of rising_edge of A, put the Do, D2...etc....for the falling_edge of A, the other ones...won't it work this way...i'm sure you know that already...did i get the question right ???
 

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