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Generating a double the source clock speed using PLL

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suddy72

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Hi everyone ,

I am using a XUP Virtex II Pro Eval Board with ISE Foundation.
I want to clock something at double the source clock speed, i have been told that this can be done using a PLL?

Does anyone know how i go about this? can this part be generated using coregen ?

Stuart
 

Re: Generating a PLL

Hi.

You can double the frequency by using DCM components inside your FPGA.
You can generate DCM codes using Architecture wizard in Xilinx ISE.

While simulating DCM's see that ur simalator resolution is set to ps.

Hope it helps.

Thanks
 

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