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need an idea on CMOS power amplifier

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nk_me

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1Mhz 0db bandwidth,800u idle current .
The opamp is used to drive 8ohm resistive load.
who can give me a sugestion about the circuit structure?
 

Why don't use the classical scheme:
Differential pair input with dynamic load - second common emitter stage (otional) - output common collector stage.
All the stages feed using current mirrors. Adjust transistor area factor for desired current rates.
By the way motorola site has application notes with examples of such a design - try to look through them. Good luck!
 

thank u first,
U give a good idea,but this power amplifier should be a cmos design,not bipolar or bicmos.
This amplifier shoud have a output stage to deliver current to load and bias circuits to stable the quiecent current in output stage. It will be implemented in 0.25um standard CMOS process.For noise consideration,it should has a p-type input differential pair.
I will read the application notes for solutions.
Happy weekend!
 

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