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25th September 2007, 11:44 #1
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vhdl integer
How can I convert a vector of say STD_logic_vector into an integer?

25th September 2007, 13:53 #2
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vhdl integer to vector
signal int : integer:
signal myvector : std_logic_vector(n downto 0)
int <= conv_integer('0'&myvector) ; for unsigned conversion
int <= conv_integer(myvector);  for signed conversion
Hope it helps
Kr,
Avi
http://www.vlsiip.com

24th June 2008, 21:13 #3
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vhdl vector to integer
and how to convert an integer to std_logic_vector given that I don't want to use std_logic_arith as it's obsolute ?

24th June 2008, 21:13

24th June 2008, 21:44 #4
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numeric_std bit vector
Of course, you can use ieee.numeric_std instead of ieee.std_logic_arith. But as a fact, most vendor packages are still based on std_logic_arith. I prefer it, too. The above conversions are also from std_logic_arith.
integer to std_logic_vector conversion needs to clarify the intended numeric representation first, so you can either use TO_SIGNED() or TO_UNSIGNED() first, casting the result to STD_LOGIC_VECTOR:
slvsignal <= STD_LOGIC_VECTOR(TO_UNSIGNED(intval,bitlen));

24th June 2008, 21:44

24th June 2008, 22:46 #5
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vhdl vector
Originally Posted by FvM

25th June 2008, 09:14 #6
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vhdl to integer
all conversion functions are described here for both numeric_std and std_logic_arith

25th June 2008, 09:14

25th June 2008, 10:17 #7
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vhdl cast integer
Originally Posted by firefoxPL

25th June 2008, 11:07 #8
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vhdl integer vector
There is no function "to_stdlogicvector" concerning integers. There is one, but this is to go from bit_vector to std_logic_vector. Bit_vectors are "arrays of bit" and defined in the VHDL standard library. But because the type "bit" is only ('0','1') it is hardly ever used, std_logic has augmented it.
There are castings from similar types to each other. Similar types are types that have a common ancestor. std_logic_vector, unsigned and signed have a common ancestor: "array of std_logic". So they are closely related and the builtin casting can be used: uns_sig <= unsigned(stdvec_sig) and stdvec_sig <= std_logic_vector(uns_sig). Builtin casting means just write the destination type and parentheses: destinationtype(...thing to be cast...)
integer (and subtypes natural and positive) are also closely related so you can cast between these: e.g. integer(0natural(positive(3)))
But the "array of std_logic"types are not closely related to the "integer"types, so special conversion functions, defined in the IEEE packages are used. For numeric_std (the one and only official IEEE package! Please help stamp out the obsolete packages and only use numeric_std!) these are called to_something, with something="unsigned" or "signed". There is no to_std_logic_vector because this would not make sense. A std_logic_vector is supposed to be a collection of std_logics that doesn't represent a number. If you want to represent a number the "unsigned" and "signed" types are used, and this automatically makes it clear which representation should be assumed when converting (sign bit or not).
So if you really need to go from integer to a std_logic_vector, you first convert using a conversion function to whatever you want the representation to be (signed or unsigned). Then, you can use a builtin cast to interpret it as a std_logic_vector.
If the thing you represent is a number, it would of course be better to keep the signed or unsigned type. It is exactly the same vector as a std_logic_vector, but it retains the concept of "number", and you can do numberlike things on them.
Personally I only use std_logic_vectors for
 groups of std_logics that are not a number, e.g. bitmasks, status bits, ...
 toplevel I/O buses because synthesis tools have a tendency to write out netlists with "std_logic_vector" for buses, even if the original VHDL code specifies "signed" or "unsigned". This way, the synthesised netlist still plugs into the testbench without having to write wrappers.

25th June 2008, 12:06 #9
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integer vhdl
Originally Posted by vomit

25th June 2008, 12:17 #10
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vhdl convert std_logic to integer
Depends on what you call lowlevel modules. Of course, if the module exists already (IP cores, wizardgenerated modules), then i just stick with that.
But for my own entities, yes, I define subtypes based on unsigned/signed.
This also provides for some additional type checking and easy naming of signals of that type:
Code:package myentitypack is subtype t_AddressBus is unsigned(9 downto 0); subtype t_DataBus is std_logic_vector(7 downto 0); component myentity is ... port ( Address : t_AddressBus; Data : t_DataBus; ... ); end component myentity; end package myentitypack;
The trick with subtypes: compare it with C code, where you can use "int" everywhere, or make auxiliary typedefs to add additional typesafety to some functions. By adding typedefs you make sure the user doesn't misuse a function outside the way it is intended. If the user wants to use some other std_logic_vector that happens to have the same length as a DataBus, he will be required to cast it "t_DataBus(myvector)" to confirm that this is really the intention and not a coincidence. This is good software practice.

25th June 2008, 13:14 #11
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integer to unsigned vhdl
What do you think if one uses std_logic_vector extensively and whenever he wants to carry out any numberbased operation, he typecasts this std_logic_vector to a signed or unsigned type .. won't that remove all the types/subtypes headache from your design ?
For example, you define a signal as x:std_logic_vector .. and y:std_logic_vector .. then do the following:
z <= signed(x) * signed(y);
or
z <= unsigned(x) * unsigned(y);
?
and in what cases do you need to use the libraries, std_logic_signed and std_logic_unsigned ?

25th June 2008, 13:14

25th June 2008, 13:53 #12
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integer vector vhdl
Whether or not it's a headache depends on what you're used to.
I'm used to seeing signed and unsigneds everywhere. So whenever I need the number there's a big chance I won't have to convert at all. After all, it's a number, so there is a big chance I'll do arithmetic on it (+1, load a counter with it, ...). The counters are of course also built out of unsigneds, after all they are numeric by definition.
It's more the opposite: on occasion I have to cast an unsigned to a std_logic_vector to interface with IP cores and toplevel I/O pins. Or to concatenate them into a microcontroller visible register where the "numeric" aspect is no longer valid. Casting can also be done within port maps, so it doesn't necessarily take auxiliary signals.
What you describe (having std_logic_vectors everywhere and casting locally) works perfectly, but is perhaps more dangerous (you have to decide/remember locally if the std_logic_vector is representing a signed or unsigned). I prefer to have dedicated subtypes to remind me for each signal type what it is: the range and (un)signedness. Whenever I need to go from 'apples' to 'oranges' I'm forced to think if and how they are compatible. This is an extra type safety. After all, that's why VHDL/ADA are strongly typed languages: to avoid mistakes.
My reasoning is simple and coherent: if it's an array of std_logics that represent a number without sign bit, don't use std_logic_vector but unsigned. Because that's exactly what unsigned was meant for. The same reasoning applies for signed. That way the entire meaning of the vector is contained in the type of the signal. This benefits readability and understandability.
Furthermore, there are some nice functions like "resize()" that work on signed and unsigned, and automatically take care of '0' or sign bit extension depending on the parameter type.
http://www.eda.org/rassp/vhdl/guidelines/1164qrc.pdf has a nice compact overview of the numeric_std library. Please throw away page 2 of that PDF, those are all vendorspecific packages, not IEEE.
Little remark: §2.4 "conversion functions" also calls the builtin cast operations (3 first items of §2.4) a "conversion function", this is strictly speaking not correct.

25th June 2008, 14:03 #13
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Now, to conclude, it looks to me like I don't need from IEEE except std_logic_1164 and numeric_std .. Am I correct ? those at least are enough for all basic operations ..

25th June 2008, 14:15 #14
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Quite correct.
http://www.cs.umbc.edu/help/VHDL/stdpkg.html
There is an official IEEE.math_real package, but I only use that for testbenches, more specifically for the nice random number functions.
There is also the IEEE.std_logic_textio for testbenches, but hasn't got anything to do with our discussion.
Don't use the signed/unsigned lookalikes from IEEE.std_logic_arith, IEEE.std_logic_signed or IEEE.std_logic_unsigned, these are obsoleted by IEEE.numeric_std.

28th June 2008, 13:55 #15
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vhdl unsigned vector
hi.
go to conversion function in language templet
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