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question related to microprocessorrs 8086

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vjfaisal

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hi

if we have asked to design a sytem with more than 64k i/o ports, so what i have to do for the following specificatin.




best regards
 

I'd multiplex the inputs. Use latches to keep the input then divide this input and feed your processor's input by a different part each cycle. The input variation however should be slower than the processor's bus clock.
 

i donot understand what u tell, please clear me what you wan to say.....
 

U can easily design it using memory mapped I/O ... It can have a max of 64K ports in 8086....because single bank can have max of 64k....
 

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