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How to use two seven segment display on FPGA board?

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vjfaisal

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hi

please tell how to use two seven segment display on FPGA board.
please tell full procedure, HOw to use it (theritically)....., if possible tell me how to implement on the board.


best rgards
 

need help in Xilinx

It depends on the board design. Which FPGA board do you have? Can you show us the schematic?
Do you plan to design the logic in Verilog, VHDL, or something else?
 

Re: need help in Xilinx

Connect display pins on board pins, and then create pulses chosen board pins, in the way You wish display to shine :).
 

Re: need help in Xilinx

im using spatarn 3 board, and i just want to code in verilog to display like the digital watch .

So, there will be two or three sevevn segment working .
what i need to do with the board to display mins, sec and hrs of digital clock.
please give your answer in therotical, what to do with this

please help ,if possible upoad the code also ......

best regards
 

need help in Xilinx

You didn't say exactly which board you have, so here's an example that builds in Xilinx ISE 9.1i and runs on the Xilinx/Digilent Spartan-3 Starter Kit.

The "hex_display" module displays a 16-bit hex value on the board's multiplexed 4-digit LED display, with adjustable brightness. The "top" module assigns the FPGA pins and includes a simple 16-bit up-counter that runs slowly so you can see it counting. You can change the counter to your time-of-day clock.

This board uses a multiplexed LED display. The four "digit" pulses illuminate each digit in sequence. The "bright" value changes the pulse width to control the brightness. The eight "segment" signals illuminate the various segments. The board's user manual has more info in the chapter "Four-Digit, Seven-Segment LED Display":
**broken link removed**

You may need to widen your web browser to avoid long-line wrap.
Code: 
module hex_display (clk, data, bright, digit, segment);
  parameter         cbits = 10;
  input             clk;
  input      [15:0] data;
  input       [3:0] bright;
  reg   [cbits-1:0] count = 0;
  wire        [3:0] nibble;
  output reg  [3:0] digit = -1;
  (* ROM_STYLE="DISTRIBUTED" *) output reg  [7:0] segment = -1;

  assign nibble = data >> ((count[cbits-1:cbits-2] ^ 3) << 2);

  always @ (posedge clk) begin
    count <= count + 1;
    digit <= ~(count[cbits-3:cbits-6] < bright ? 8 >> count[cbits-1:cbits-2] : 0);
    case (nibble)
       0: segment <= ~8'b11111100;  // "a b c d e f g h"
       1: segment <= ~8'b01100000;
       2: segment <= ~8'b11011010;  //   --a--
       3: segment <= ~8'b11110010;  //  |     |
       4: segment <= ~8'b01100110;  //  f     b
       5: segment <= ~8'b10110110;  //  |     |
       6: segment <= ~8'b10111110;  //   --g--
       7: segment <= ~8'b11100000;  //  |     |
       8: segment <= ~8'b11111110;  //  e     c
       9: segment <= ~8'b11110110;  //  |     |
      10: segment <= ~8'b11101110;  //   --d--  (h)
      11: segment <= ~8'b00111110;
      12: segment <= ~8'b10011100;
      13: segment <= ~8'b01111010;
      14: segment <= ~8'b10011110;
      15: segment <= ~8'b10001110;
      default: segment <= 8'bx;
    endcase
  end
endmodule


module top (clk, LED_Digit, LED_Segment);
  (* LOC="T9",PERIOD="50 MHz" *) input clk;
  (* DRIVE="4",LOC="E13,F14,G14,D14" *) output [3:0] LED_Digit;
  (* DRIVE="4",LOC="E14,G13,N15,P15,R16,F13,N16,P16" *) output [7:0] LED_Segment;
  reg  [37:0] count = 0;

  hex_display hex1 (.clk(clk), .data(count[37:22]), .bright(4'd5), .digit(LED_Digit), .segment(LED_Segment));

  always @ (posedge clk)
    count <= count + 1;
endmodule
 

Re: need help in Xilinx

ya here in pakistan, we have Xilinx 8.1i version , but still im not clear with your argue.... How i could display the time just like digital clock, for mins secs and hrs,

please clear me these .... how to diplay a time on the board



best regards
 

need help in Xilinx

Change the "count" binary counter to a suitable decimal counter.

Which board do you have?
 

Re: need help in Xilinx

i have Xilinx ISE 9.1i and Xilinx Spartan-3 Starter Kit ,
now to do, please explain
 

need help in Xilinx

That board has a 4-digit display. It can't display hours, minutes, and seconds, at least not all simultaneously.

Here are two digital clock examples from Xilinx:
**broken link removed**
 

Re: need help in Xilinx

OK, first check the frequency of Your clock generator. Calculate how many pulses clock creates for one second (let's say N pulses for one second). Then, create counter from 0 to N-1, and each time it gets to state "all zeroes", You should make signal "one second" active for one clock period. With this signal You control 7 signals for Your 7-segment display that represents seconds, in form of LUTs (meaning You create code in manner "... if "one second" is active, and previous state of 7 signals was code for "4", then next state for 7 signals is code for "5", etc...."). Then, create one more counter from 0 to 59 to count how many times the rising edge of "one second" occurs. Let's call this signal "one minute". In the same manner as above, use this signal to control 7-segment display that represents minutes. Finally, use one more 0..59 counter to count the number of "one minute" pos. edges => "one hour" signal => 7-segment display for number of hours.

And You should count the number of hours from 0 to 11, or from 0 to 23, to make sure everyone knows how to read time from Your digital clock :).
 

Re: need help in Xilinx

kindly post me the code for it....

i need to implement it......
 

Re: need help in Xilinx

echo47 said:
That board has a 4-digit display. It can't display hours, minutes, and seconds, at least not all simultaneously.

Here are two digital clock examples from Xilinx:
**broken link removed**
Click to expand...

Hi, tried to to compile this code on Altera Quartus it has errors:
Error (12006): Node instance "clk50in_ibuf" instantiates undefined entity "ibufg_lvcmos33"
and a lot of other "... instantiates undefined entity", although i can see the statements of this instantiates.
All i did is copy paste! Can you please explain whats wrong, why these errors come up?
 

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