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Post-synthesis simulation error in modelsim-iteration limit.

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Sujatha_11

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modelsim iteration limit

Hi,
My VHDL code works fine when I do a pre-synthesis simulation. It does synthesize also. But, when I try to simulate the post-synthesis code it says iteration limit reached. vsim 3601 error. nd delay truncated. I do not understand why this is happening. If there are any infinite runnin loop or zero delay gates my pre-synthesis code also should not work right? I used modelsim SE version 6.0 for writing the code and simulating it and synthesized using xilinx ISE web pack. Please help me fix this problem. I have to meet a deadline.
Thanks in advance.

Regards,
Sujatha.
 

vhdl iteration limit is reached

Sujatha_11 said:
Hi,
My VHDL code works fine when I do a pre-synthesis simulation. It does synthesize also. But, when I try to simulate the post-synthesis code it says iteration limit reached. vsim 3601 error. nd delay truncated. I do not understand why this is happening. If there are any infinite runnin loop or zero delay gates my pre-synthesis code also should not work right? I used modelsim SE version 6.0 for writing the code and simulating it and synthesized using xilinx ISE web pack. Please help me fix this problem. I have to meet a deadline.
Thanks in advance.

Regards,
Sujatha.
Click to expand...

Sujatha,
It is not uncommon, so don't worry :) This has been reported in this forum as well, see:

I believe you don't have SDF, if so are you using delay_mode_unit? If not, try that first. This is what we recommend as first thing in our CFV course when it comes to Gate Level Simulations. Details of this 1-day course are at www.noveldv.com

Regards
Ajeetha, CVC
www.noveldv.com
 

modelsim iteration

Hi Ajeetha,
I do not understadn what you are saying. What is SDF and how do I generate it or get it? I am new to FPGA/VHDL/Synthesis. This is my first project. Please help me. and delay_mode_unit where is this available? I did post-synthesis in ISE webback which gave me a VHDL file after generating the post-sysnthesis simulation model. Please let me know.
Thanks & Regards,
Sujatha.
 

post synthesis simulation xilinx modelsim

Hi
u have also specified the error number as 3601,why dont you try in the answer base of xilinx.this may help u.if u have net to your system it will directly root to the support.
 

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