regarding VREF and GCLK of banks in FPGA

hi,

i am working on virtex 2 pro fpga i have a basic doubt

1. i am using bank 5 for my input and outputs. i have vref in the bank which is not connected to supply(3.3v). my doubt is whether i should connect it to the supply voltage. if i am not using the I/O of any bank do i have to connect the VREF of that bank to the corresponidng supply voltage or i can leave as unconnected.
if u connect one pin of vref to supply voltage is enough as the other VREF are internally connected to each other.

2. what are VCCINT, VCCAUX, VCCO,VREF VIN,VTS in fpga any particular rules that need to be followd while working with them and each bank can have different
VCCAUX supply and each bank can be supplied with different GCLK (say bank 5 has GCLK5S and GCLK4P should have same supply GCLK as internally they are connected to same GCLK right).

regards
kil

1. I don't know what is there with Virtex2Pro, but always VREF pins is needed only for voltage-referenced IO standards (for example SSTL). For example in Cyclone devices you can leave these pins unconnected (or user-defined) if you use single-ended IO standards (LVTTL, etc...). But in Stratix your have to connect VREF to corresponded supply.

2. VCCINT - supply for core circuits of FPGA (always IO and core circuits use different supply)

VREF - refference voltage, for voltage-reference IO supply

For clear description read associated documents at xilinx.com