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Corner cases for DDR verification

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asicengineer1

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Hi all,
I'm about to start verifying a DDR-sdram controller. Could you suggest some corner cases to verify it ? Some of the ones which i can think of are :

1. Read burst with different burst lengths.
2. write bursts with different lengths.
3. consecutive/ nonconsecutive bursts.
4. burst terminates.

apart from these, what else can be verified in a controller module ?

Thanks.
 

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