rsrinivas
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Hi all
I have designed a filter in matlab in fdatool,got the verilog code and it's working fine.
now i need to have a bank of filters(16) using this single filter.i have developed a simple architecture like having the coefficients in a rom and the filter internals in a dpram ,an address generator ,a fifo to dump the filter outputs and a simple controller.i.e. a serial architecture.
for each filter input sample the coefficients are read and processed and the context of the filter internals are stored in the dpram.repeated 16 times
what r the considerations in this design.
will this idea work.
any suggestions greatly appreciated.
I have designed a filter in matlab in fdatool,got the verilog code and it's working fine.
now i need to have a bank of filters(16) using this single filter.i have developed a simple architecture like having the coefficients in a rom and the filter internals in a dpram ,an address generator ,a fifo to dump the filter outputs and a simple controller.i.e. a serial architecture.
for each filter input sample the coefficients are read and processed and the context of the filter internals are stored in the dpram.repeated 16 times
what r the considerations in this design.
will this idea work.
any suggestions greatly appreciated.