fm_com_28
Full Member level 1
- Joined
- Feb 2, 2006
- Messages
- 99
- Helped
- 11
- Reputation
- 22
- Reaction score
- 7
- Trophy points
- 1,288
- Location
- Fayoum, Egypt
- Activity points
- 1,916
vhdl comparator
I want to design a 2-bit comparator using VHDL that takes two unsigned std_logic_vectrors A and B and produces bits L,G,E, where
L=1 , if A<B
G=1, if A>B
E=1, if A=B
Then Using VHDL, I want to design an 8-bit comparator that uses the 2-bit .the 8bit comparator should have two 8-bit registers that load the inputs on the rising edge of the clock and one 3bit register that loads the outputs on the falling edge of the clock.
I want to design a 2-bit comparator using VHDL that takes two unsigned std_logic_vectrors A and B and produces bits L,G,E, where
L=1 , if A<B
G=1, if A>B
E=1, if A=B
Then Using VHDL, I want to design an 8-bit comparator that uses the 2-bit .the 8bit comparator should have two 8-bit registers that load the inputs on the rising edge of the clock and one 3bit register that loads the outputs on the falling edge of the clock.