kslim
Newbie level 5
Regardless of whether to use it or not, I have a code that contains huge internal tristate bus, and almost for sure I have(or wish) to reuse the entire code. In RTL, there is a specific Pullup verilog keyword to drive the bus high when tristate buffer is disabled.
Does DC understand this Pullup statement to infer some resitive element to pull up the bus? I figured not, and started to wonder how to infer pull up resistor in asic flow.
Does DC understand this Pullup statement to infer some resitive element to pull up the bus? I figured not, and started to wonder how to infer pull up resistor in asic flow.