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internal tristate bus

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kslim

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Regardless of whether to use it or not, I have a code that contains huge internal tristate bus, and almost for sure I have(or wish) to reuse the entire code. In RTL, there is a specific Pullup verilog keyword to drive the bus high when tristate buffer is disabled.

Does DC understand this Pullup statement to infer some resitive element to pull up the bus? I figured not, and started to wonder how to infer pull up resistor in asic flow.
 

Well, DC is not the only problem, and still with Formality, DFT, STA remains.

as for DC, the key problem is logic mapping and libray preparation.

Besides, i dont believe adding Tristate logic would benifet a lot, regarding the timing, power, and area.
 

Hi ,

I saw I/O cells have these capabilities , which are fully custom cells .
But i don't think we can do the same in RTL code ?

Thanks & Regards
yln
 

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