samuel_raja_77
Junior Member level 2
1.i need to enable module2 from module1 and.....after finishing some operation i need to disable the module2 from processing .....and continue the manipulation in module1
2.i tried like giving an enable signal [en_1 o/p from module1] from module1 to module2 such that if that enable signal is high the module2 will be processing .....after finishing stipulated process another enable signal [en_2 o/p from module2] will be made high stating the process is over.
3.so when en_2 is high which is input to module1 the en_1 will be made low..thus enabling the module1
4.so if i need to again enable the module2 i need to make the en_2 to be low in the second module ........
5.Is the propsed method right to use in verilog can some one guide me
2.i tried like giving an enable signal [en_1 o/p from module1] from module1 to module2 such that if that enable signal is high the module2 will be processing .....after finishing stipulated process another enable signal [en_2 o/p from module2] will be made high stating the process is over.
3.so when en_2 is high which is input to module1 the en_1 will be made low..thus enabling the module1
4.so if i need to again enable the module2 i need to make the en_2 to be low in the second module ........
5.Is the propsed method right to use in verilog can some one guide me