Synchronization of External clock with Internal in PIC

In Using Timer0 with External Clock, it is said that

The synchronization of T0CKI with the internal phase clocks is accomplished
by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns).

Similarly, in T1CON register, you have a Timer1 External Clock Input Synchronization Control bit.
How is this synchronisation done & why is it necessary...
Kindly help

This is exactly how it is accomplished:

elexhobby said:

by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks.

Click to expand...

Why it is necessary? It is not really "necessary", but it happens, because the micro is in fact a sequential circuit, that is, it only does one thing at a time, so it will "look" ("sample") at these signals only once or twice every instruction cycle.

Sort of like you looking at your watch, when you are expecting impatiently a package to be delivered: the watch works all the time, but you only look at it once in a while, because you have other things to do, too. In effect you "sample" the time to see when that much-awaited package arrives.
So you will not see the watch all the time and it is possible to "miss" the exact moment, but nevertheless, you will see that the time is up next time you consult your watch. You can then act (with a short delay) and proceed to go pick up your parcel.

If you look at your watch every 3 minutes and you check your watch at 9:58 and the parcel arrives at 10:00, then you will know it has arrived only at 10:01, when you check your watch. It is only then that you take action and go pick up the parcel. In effect, you have "synchronized" your next action (parcel pickup) with your watch (if you were a micro, this would be your "clock": 3 min period).

Now imagine the delivery guy is there only for a while. If he stays for less than 3 minutes, you may well miss him, because you only check your time every 3 minutes.

Hi VVV..
Thanks for such a wonderful & lucid explanation.
I have a few doubts. Please clear them.
First, tell me whether what I understand by Q2 & Q4 is right or wrong… The PIC divides crystal freq by 4, so for every 4 pulses of clock, there will be one pulse of “PIC”. & I thought, the rising edges of 2nd & 4th pulses of the “crystal” clock are designated as Q2 & Q4 respectively. This is how it is for 8051. Am I right in understanding this?
Secondly, if the sampling scheme is as said, then the max frequency of the prescaler output can be 5 Mhz for a 20 Mhz external clock.. & since the prescaler can be set to a max value of 256, the max freq that can be measured is 256*5 MHz = 1280 MHz !!! Is this true?

Added after 11 minutes:

Hi VVV..
Thanks for such a wonderful & lucid explanation.
I have a few doubts. Please clear them.
First, tell me whether what I understand by Q2 & Q4 is right or wrong… The PIC divides crystal freq by 4, so for every 4 pulses of clock, there will be one pulse of “PIC”. & I thought, the rising edges of 2nd & 4th pulses of the “crystal” clock are designated as Q2 & Q4 respectively. This is how it is for 8051. Am I right in understanding this?
Secondly, if the sampling scheme is as said, then the max frequency of the prescaler output can be 5 Mhz for a 20 Mhz external clock.. & since the prescaler can be set to a max value of 256, the max freq that can be measured is 256*5 MHz = 1280 MHz !!! Is this true?

The PIC does not simply divide the crystal frequency by 4, rather each instruction takes 4 oscillator periods to complete (actually, it appears that way because of the pipelined adrchitecture, else it would take eight, like the goto instructions). Each of these corresponds to states, named Q1,...Q4. It is similar to the 8051, yes.

No, the maximum input frequency is limited by the hardware and I think it is 50 MHz when using the prescaler. Check the datasheet of your PIC. But 50 MHz is still a respectable frequency limit.