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need help in verilog programming

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hi.
I'm a beginner and in my design I need a register ( or anything that can hold my data ) that is both readable and writable from two modules. what should I do?
thanks in advance.
 

you can create a buffer of inout type for the register and pass it as argument to the two modules

regards
 

1. Read is easy since it is output from your register. All you need is branch the data out to the data input of your modules.

2. Write need arbitration. You should prioritize your modules, or have a fairness engineer to even the access right for each module. The arbitration logic would switch write access for your module, depends on the rule you formed.

Henry
 

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