the working principle of the switch-cap CMFB

HI all:
who can tell me the working principle of the switch-cap CMFB.I have found so many books or papers,but i didn't get the satisfied answer for they all said so:capacitor cs is used to sample the voltage difference between the expected output common mode voltage and the vref which is used to bias the tail current source.the capaitor Cc is used to generate the average output voltages.but this is not enough if i want to find the capacitors's parameter.so my questions are:
1) who can tell me the pinciples in details,how the charge on the cpacitors is distribued and transfered in tow clock phase.especially the dc voltage and the small ac voltage across the capacitors.
2)what's the relationship between the CMFB loop and the main AMP.in my opinion,this relationship can give the capacitors's parameter.
any answer is welcome,any books or papers which can give these anwsers are prefered.
ps:the attachment is the repesentative circuits of the switch-cap CMFB,in which cm=cs,ccm=cc.
thanks!

A few points about your schematic, which you did not draw correctly:

1) CSH capacitors: they can not be connected at the first stage outputs to the second stage gate inputs. If you do so, the second stage would be floating and no DC bias;

2) The CMFB switches are not drawn correctly as well. You may refer to any books which descirbe this SC CMFB common topic.

Firstly in the main circuit, the Cc is for Compensation purposes. The CSH i sfor level shifting so that the output can be driven by the NMOS stages.

Secondly, in the CMFB, there is a Vref which is used for comparision. On the LHS of the CMFB circuit, you will see the Vref. On the RHS, the capacitors, will be switched between, Vref and VCM0. The VCM0 is the ideal value of the Output common mode voltage. Hence, the output of the CMFB circuit will actually see a current differential due to the difference between (VCM0 -(V0+ + V0-)/2). Remember that since Vref is common to both the differential pairs of the CMFB, there is no current due to the Vref.

I hope that I am clear

the first problm i agree with you.second problem maybe not an issue.in the common sense,the vref and vcmo are controled by a switch,but this is not so important when you analyze the circuit.becase the cm can be seen as a voltage source for ccm i guess.can you give me some books names which describe sc CMFB topic?
ps:the circuit is not drawned by me,i got the circuit from the internet.so....

willyboy19 said:

A few points about your schematic, which you did not draw correctly:

1) CSH capacitors: they can not be connected at the first stage outputs to the second stage gate inputs. If you do so, the second stage would be floating and no DC bias;

2) The CMFB switches are not drawn correctly as well. You may refer to any books which descirbe this SC CMFB common topic.

Click to expand...

Added after 35 minutes:

i can't understand so clearly.let me decribe my understanding of the circuit, and you can correct my fault.
commonly,the circuit works on two non-overlaped clocks.we set clk1 and clk2
when clk1 is high,the capacitor cm is conneced to vcmo and vref.
when clk2 is high,then capacitor cm and capacitor ccm are paralled and are connected to vo+ ,vo-,and the gate of the current source.
so,when clk1 is high,the charge on the cm is cm*(vcmo-vref).then at this time,what is the dc value of the gate voltage of the current source(also refer the outupt of the CMFB).
when clk2 is high,then the charge on the capacitor cm will be distributed on capcitor cm and ccm.so i can' understand the dc volatage across the ccm is what?

Vamsi Mocherla said:

Firstly in the main circuit, the Cc is for Compensation purposes. The CSH i sfor level shifting so that the output can be driven by the NMOS stages.

Secondly, in the CMFB, there is a Vref which is used for comparision. On the LHS of the CMFB circuit, you will see the Vref. On the RHS, the capacitors, will be switched between, Vref and VCM0. The VCM0 is the ideal value of the Output common mode voltage. Hence, the output of the CMFB circuit will actually see a current differential due to the difference between (VCM0 -(V0+ + V0-)/2). Remember that since Vref is common to both the differential pairs of the CMFB, there is no current due to the Vref.

I hope that I am clear

Click to expand...

First What a bunch of typical "look I know the answer to your question let me see if I can half confuse you with my answer to lure you to believe I actually understand the botton of this". The typical engineering crowd. Williboy, why do you stop at pointing errors ? The cmfb switched cap difference equation is -NOT- in just any textbook. Vamsi, your superficial answer is within the grasp of any average schooled enginneer, try to actually answer the question and derive the expression for the cmfb control signal. You two gave up before even trying.

I think this paper will satisfy you: 'analysis of switched-capacitor common-mode feedback circuit', written by Ojas Choksi.you can find it in IEEE website

can you upload it?
thanks

lye said:

I think this paper will satisfy you: 'analysis of switched-capacitor common-mode feedback circuit', written by Ojas Choksi.you can find it in IEEE website

Click to expand...

u can also find detail explanation in Ch12, "analysis and design of analog integrated circuits" 4th edition by Paul Gray.

I'd like to see the download file for further answer.
Thanks

common mode feedback is a function to stable the dc of output

winsonpku said:

i can't understand so clearly.let me decribe my understanding of the circuit, and you can correct my fault.
commonly,the circuit works on two non-overlaped clocks.we set clk1 and clk2
when clk1 is high,the capacitor cm is conneced to vcmo and vref.
when clk2 is high,then capacitor cm and capacitor ccm are paralled and are connected to vo+ ,vo-,and the gate of the current source.
so,when clk1 is high,the charge on the cm is cm*(vcmo-vref).then at this time,what is the dc value of the gate voltage of the current source(also refer the outupt of the CMFB).
when clk2 is high,then the charge on the capacitor cm will be distributed on capcitor cm and ccm.so i can' understand the dc volatage across the ccm is what?

Click to expand...

you r correct, when clk2 is high there is a charge distribution, but after many clks, let's say 10 clks, the charge distribution will be very small and cmfb will gain a stable point.
So the circuit with SC-cmfb has delay to work correctly.

Regards,

in fact, i don't think the explanation of the SC CMFB is detail enough in the book wroten by Gray.

from this schematic, i have a question: when the output common voltage varies, say a small step, this change transmits to cmfb control voltage through cm, then the control voltage regulates main circuit to draw the output common voltage back. this process is accompanied with some rings. i should how to prevent it?