Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

what's the real difference between these three command?

Status
Not open for further replies.
B

bendrift

Member level 4
Joined
Nov 18, 2004
Messages
74
Helped
5
Reputation
10
Reaction score
4
Trophy points
1,288
Activity points
688
rtl compiler impact of set_case_analysis

set_false_path
set_case_analysis
set_disable_timing
what 's the real difference between these three command?
would anyone give some example for them?
thank u :)
 

set_case_analysis set_false_path

You can have a look at the following docs which are about prime time and design compiler.
There are some examples for the set_case_analysis command and explain the difference between the set_false_path and set_disable_timing.
 

set_disable_timing -through

set_false_path : Telling tool to ignore the path
set_case_analysis : Telling tool to assume "constant" value on port/pin
set_disable_timing : Telling tool to disable the timing arc .
 
  • Like
Reactions: ivlsi

    ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating
set_case_analysis example

i think:
set_false_path caculate the timing arc,but set the these in timing exceptions.
set_case_analysis and set_disable_timing didn't caculate the timing arc.
is it right?
 

set_disable_timing

set_false_path : deal with a path that cant transform a signal.
set_case_ana : deal with when 1 are critical path when 0 are dont care path
set_disable : deal with you dont want timing engine to calculate the path.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top