javierh.santiago
Junior Member level 2
Greetings,
How can I report timing in prime time using multiple libraries for a combinational circuit?
I am using following commands, where "complete.db" is a library that would consider aging effects in the circuit. So, I would expect that prime time gives me a longer timing (but the optimal clock frequency) in order to ensure reliability after several years.
set link_path " NangateOpenCellLibrary.db complete.db "
read_verilog nBitAdder_netlist.v
link_design nBitAdder_netlist
However, when I do "check_timing" or "report_timing", the tool says "No constrained paths". Does anyone can provide some advises? Seems that I have to indicate some constrains, but as this circuit is pure combinational, I am not sure which ones.
P.S. Netlist is just a simple adder, C = a+b, I just need to start using aging library and prime time prior beginning my research project
Regards,
How can I report timing in prime time using multiple libraries for a combinational circuit?
I am using following commands, where "complete.db" is a library that would consider aging effects in the circuit. So, I would expect that prime time gives me a longer timing (but the optimal clock frequency) in order to ensure reliability after several years.
set link_path " NangateOpenCellLibrary.db complete.db "
read_verilog nBitAdder_netlist.v
link_design nBitAdder_netlist
However, when I do "check_timing" or "report_timing", the tool says "No constrained paths". Does anyone can provide some advises? Seems that I have to indicate some constrains, but as this circuit is pure combinational, I am not sure which ones.
P.S. Netlist is just a simple adder, C = a+b, I just need to start using aging library and prime time prior beginning my research project
Regards,