manishpatkar
Junior Member level 1
i am trying to code adpll on xilinx vivado , i am not ble get the logic for kcounter loop filter! if someone can help me atleast with the logic or code, it would be really helpfull!
my pfd code is here
i have found this code for loop filter , but can't seem to understand it! its down here , can someone explain the logic ?
I have attached the block diagrams of first two blocks
**broken link removed****broken link removed**
my pfd code is here
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/27/2017 12:01:45 AM
-- Design Name:
-- Module Name: pfd1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pfd1 is
Port (
A : in STD_LOGIC;
ref : in STD_LOGIC;
div : in STD_LOGIC;
UP : out STD_LOGIC;
DOWN : out STD_LOGIC);
end pfd1;
architecture Behavioral of pfd1 is
signal up1 , down1 , reset :std_logic;
component dff is
Port (
D : in STD_LOGIC;
clk : in STD_LOGIC;
sync_reset : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
begin
D1 : dff
port map
(
D => A,
clk => ref,
sync_reset => reset,
Q => up1
);
D2 : dff
port map
(
D => A,
clk => div,
sync_reset => reset,
Q => down1
);
reset <= up1 and down1;
UP <= up1;
DOWN <= down1;
end Behavioral;
i have found this code for loop filter , but can't seem to understand it! its down here , can someone explain the logic ?
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY loop_filter IS
-- Declarations
port ( CLK : in std_logic;
RESET : in std_logic;
C : in signed(7 downto 0);
D1 : out signed(11 downto 0);
D2 : out signed(11 downto 0)
);
END loop_filter ;
ARCHITECTURE behavior OF loop_filter IS
signal E : signed(11 downto 0);
signal dtemp : signed(11 downto 0);
begin
process(CLK, RESET)
begin
if (RESET='1') then
D1 <= (others => '0');
D2 <= (others => '0');
E <= (others => '0');
dtemp <= (others => '0');
elsif rising_edge(CLK) then
dtemp <= (C(7)&C(7)&C(7)&C&'0') + dtemp - E;
E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4);
D1 <= dtemp;
D2 <= dtemp(11 downto 4)&"0000";
end if;
end process;
END behavior;
I have attached the block diagrams of first two blocks
**broken link removed****broken link removed**