Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Writing SDC constraints for Asynchronous clocks

Status
Not open for further replies.

krishh9

Newbie level 4
Joined
Mar 19, 2010
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
pune
Activity points
1,312
Hello All,

I am new to SDC constraints,
in synchronous clock definition
If A is input port and B is output pin then we can define create_clock on A and generated_clock on B with divide_by option.

Now say X is input and Y is output, and both are asynchronous with each other.
Where such scenario will come in design and how to write SDC constraints on input and output?

Thanks in advance
 

This doesn't sound possible. Y has to be related to some clock. if you create a generated clock on Y, it will 'inherit' Y's clock.

Maybe I misunderstood what you are asking.
 

The generated clock has to be dependent of the source clock , else the other possibility is when one of the flops has a clock that is generated using combinatorial logic of some other input pins , then you might have a scenario of Asynchronous clocks; But that kind of design is never encouraged and to fix timing on such flops is a nightmare.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top