Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Request for a basic verification code example in Verilog

Status
Not open for further replies.

bit_an

Junior Member level 3
Joined
Mar 11, 2017
Messages
28
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
235
Dear All,

I am a student with primitive experience in verilog. I have a small verification task for a top module. I have simplified the task in the below description, so that you can give me a quick response. There could be solve for this problem in various ways. But ideally I am finding a solution to create an automatic test setup.

Please find below the problem. If you could write me a solution with a working example in verilog, that would be a good starting point.

Write a Script or Test bench for the following tasks;
Send Data = 8 bits and Received Data is 16 bits.

1. First Send Data for 0-256 data frames with STATUS_IN = 0, and then again Send Data 0-256 data frames with STATUS_IN = 1
2. Next send few control frames of 8 bits with specific pattern (e.g. 8'b00110101) again with STATUS_IN = 0 and STATUS_IN = 1
3. Compare if Send Data == Received Data at the DATA_OUT port. Also compare if STATUS_IN == STATUS_OUT for every received data frame
4. Print SUCCESS or FAIL for every data frame transmission in a File (use File handling)
File handling: Print Send Data and Received Data, Print STATUS_IN and STATUS_OUT and SUCCESS and FAIL for each data frame transmission

One additional task is to breaking 16 bits Received Data in two 8 bits for each cycle. Find attached the diagram of the module.

verify_test.JPG

Thanks and Regards,
 
Last edited:

you have broken down the problem already, why didn't you try to implement a testbench for it?
 

I am trying. I am using multiple initial blocks in the testbench. This makes the structure bulky and introduce scheduling issues. Looping over sending data is fine. But additional control words are not done yet.. Since its an easy problem, I thought of asking, to know if there is a better approach.
 

I am trying. I am using multiple initial blocks in the testbench. This makes the structure bulky and introduce scheduling issues. Looping over sending data is fine. But additional control words are not done yet.. Since its an easy problem, I thought of asking, to know if there is a better approach.
Yeah the easier way is to write Bus Functional Models (BFMs) to send data and receive data (check rx data). Then you can write the model using tasks instead of sticking all the signals assignments inside of initial blocks. The way you are approaching this is the brute force wiggle pins approach, which is not very efficient and can result in those pesky scheduling issues. It is also very inflexible, and making changes can result in ripple effects where you have to change half of your code (all the time offsets) to add a single extra signal toggle.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top