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Problem facing in Xpower Analyzer

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qaziarbab

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Hi,

I am using Xilinx ISE (13.61) to implement my design into FPGA. I want to analyze the dynamic power of my circuit, preferably, component wise. I have uploaded my (.ncd, .pcf and .vcd) files in Xilinx Xpower analyzer, but I am facing the following error.
"ERROR:power:1976 - $scope with no corresponding $upscope ERROR:power:85 - Error reading VCD file, no simulation data will be applied."
Could you please help me how can I rectify the error to proceed my work.
Thanks
Regards, Qazi
 

your vcd file seems to be corrupted

But I have done several times and several with versions of vcd of different designs. What could be the problem with my VCD? After implementing, I have ran simulations for certain time (30ms) and obtained the vcd. I have attached one of the vcd file. If you could look at it?

Qazi ..
 

Why would you send this as a doc file, nobody with any sense will open that file.
 

Stripping everything but the $scope-$upscope heirarchy....there seems to be a problem with your output.

Code:
$scope module testbench $end
  $scope module uut $end
    $scope module mc8051 $end
      $scope begin \gen_mc8051_siu(0)\ $end
        $scope module i_mc8051_siu $end
        $upscope $end
      $upscope $end
      $scope begin \gen_mc8051_tmrctr(0)\ $end
        $scope module i_mc8051_tmrctr $end
        $upscope $end
      $upscope $end
      $scope module i_mc8051_control $end
      $upscope $end
      $scope module i_control_mem $end
        $scope begin \for_tmr(0)\ $end
        $upscope $end
        $scope begin \for_siu(0)\ $end
        $upscope $end
        $scope begin \for_intext_edge(0)\ $end
        $upscope $end
        $scope begin \for_tf_edge(0)\ $end
        $upscope $end
        $scope begin \for_siu_edge(0)\ $end
        $upscope $end
      $upscope $end
    $upscope $end
    $scope module i_mc8051_alu $end
      $scope begin gen_multiplier1 $end
        $scope module i_comb_mltplr $end
        $upscope $end
      $upscope $end
      $scope begin gen_divider1 $end
        $scope module i_comb_divider $end
        $upscope $end
      $upscope $end
      $scope begin gen_dcml_adj1 $end
        $scope module i_dcml_adjust $end
        $upscope $end
      $upscope $end
      $scope module i_alumux $end
      $upscope $end
      $scope module i_alucore $end
      $upscope $end
      $scope module i_addsub_core $end
        $scope begin gen_greater_four $end
          $scope begin \gen_addsub(1)\ $end
          $upscope $end
          $scope begin \gen_addsub(2)\ $end
          $upscope $end
          $scope begin \gen_addsub(3)\ $end
          $upscope $end
          $scope begin \gen_addsub(4)\ $end
            $scope begin gen_nibble_addsub $end
              $scope module i_addsub_cy $end
              $upscope $end
            $upscope $end
          $upscope $end
          $scope begin \gen_addsub(5)\ $end
            $scope begin gen_last_addsub $end
              $scope module i_addsub_ovcy $end
                $scope begin gen_greater_one $end
                $upscope $end
              $upscope $end
            $upscope $end
          $upscope $end
          $scope begin \gen_addsub(6)\ $end
          $upscope $end
          $scope begin \gen_addsub(7)\ $end
          $upscope $end
          $scope begin \gen_addsub(8)\ $end
          $upscope $end
        $upscope $end
      $upscope $end
    $upscope $end
  $upscope $end
  $scope module Interal_RAM $end
    $scope module U0 $end
      $scope begin no_input_stage $end
      $upscope $end
      $scope begin native_mem_module $end
        $scope module mem_module $end
          $scope begin async_coll $end
          $upscope $end
          $scope module reg_a $end
There seems to be a bunch of missing $upscope to for the previous $scope starting at Interal_RAM. See post #2
 
Stripping everything but the $scope-$upscope heirarchy....there seems to be a problem with your output.

Code:
$scope module testbench $end
  $scope module uut $end
    $scope module mc8051 $end
      $scope begin \gen_mc8051_siu(0)\ $end
        $scope module i_mc8051_siu $end
        $upscope $end
      $upscope $end
      $scope begin \gen_mc8051_tmrctr(0)\ $end
        $scope module i_mc8051_tmrctr $end
        $upscope $end
      $upscope $end
      $scope module i_mc8051_control $end
      $upscope $end
      $scope module i_control_mem $end
        $scope begin \for_tmr(0)\ $end
        $upscope $end
        $scope begin \for_siu(0)\ $end
        $upscope $end
        $scope begin \for_intext_edge(0)\ $end
        $upscope $end
        $scope begin \for_tf_edge(0)\ $end
        $upscope $end
        $scope begin \for_siu_edge(0)\ $end
        $upscope $end
      $upscope $end
    $upscope $end
    $scope module i_mc8051_alu $end
      $scope begin gen_multiplier1 $end
        $scope module i_comb_mltplr $end
        $upscope $end
      $upscope $end
      $scope begin gen_divider1 $end
        $scope module i_comb_divider $end
        $upscope $end
      $upscope $end
      $scope begin gen_dcml_adj1 $end
        $scope module i_dcml_adjust $end
        $upscope $end
      $upscope $end
      $scope module i_alumux $end
      $upscope $end
      $scope module i_alucore $end
      $upscope $end
      $scope module i_addsub_core $end
        $scope begin gen_greater_four $end
          $scope begin \gen_addsub(1)\ $end
          $upscope $end
          $scope begin \gen_addsub(2)\ $end
          $upscope $end
          $scope begin \gen_addsub(3)\ $end
          $upscope $end
          $scope begin \gen_addsub(4)\ $end
            $scope begin gen_nibble_addsub $end
              $scope module i_addsub_cy $end
              $upscope $end
            $upscope $end
          $upscope $end
          $scope begin \gen_addsub(5)\ $end
            $scope begin gen_last_addsub $end
              $scope module i_addsub_ovcy $end
                $scope begin gen_greater_one $end
                $upscope $end
              $upscope $end
            $upscope $end
          $upscope $end
          $scope begin \gen_addsub(6)\ $end
          $upscope $end
          $scope begin \gen_addsub(7)\ $end
          $upscope $end
          $scope begin \gen_addsub(8)\ $end
          $upscope $end
        $upscope $end
      $upscope $end
    $upscope $end
  $upscope $end
  $scope module Interal_RAM $end
    $scope module U0 $end
      $scope begin no_input_stage $end
      $upscope $end
      $scope begin native_mem_module $end
        $scope module mem_module $end
          $scope begin async_coll $end
          $upscope $end
          $scope module reg_a $end
There seems to be a bunch of missing $upscope to for the previous $scope starting at Interal_RAM. See post #2
Hi,
I will try to fix it now. Thanks.
 

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