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Placing Low Voltage Device in High Voltage WELL

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Sanketp20

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Hi,

If I place low voltage fet in high voltage well, will that device be considered as high voltage as well ?
For example:
Let's consider 5 volt to be high volt in 28nm TSMC process. and 1.2V to be low volt.
Now if I place 1.2V pmos in 5V NWELL, will the voltage on nets connected to that pmos also considered 5V nets and should I enforce 5V metal spacing DRC rules on those nets ?
I appreciate your guidance.

Thanks
 

If I place low voltage fet in high voltage well, will that device be considered as high voltage as well ?

Not at all! The voltage tolerance of a MOSFET is mainly determined by its gate oxide thickness, not by its bulk environment.
High voltage MOSFETs need thicker gate oxide.
 

So, layout designer should not even place low voltage device in HV well right and DRC should flag if they do that ?
 

Not neccessarily. It depends on your PDK. Try putting a LV device in a HV well and run DRC. Place it next to devices that already occupy the well and make sure you add the proper pins and/or markers that may be needed.
 

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