joul
Newbie level 4
Let's say we have
Basically I want a to go to '1' if s2 is '0' and stay that way when s2 goes back to '1'.
Let's say there is no clock available.
It works as expected on a FPGA but is that considered a combinatorial loop and is it bad practice ?
Thanks
Code:
entity ent is
port (
...
...
a : out std_logic
);
end ent;
architecture archi of ent is
signal s1,s2 : std_logic;
begin
...
s2 <= <some condition>;
...
[B]s1[/B] <= '1' when s2 = '0' [B]or s1 = '1'[/B] else '0';
a <= s1;
end archi ;
Basically I want a to go to '1' if s2 is '0' and stay that way when s2 goes back to '1'.
Let's say there is no clock available.
It works as expected on a FPGA but is that considered a combinatorial loop and is it bad practice ?
Thanks