promach
Advanced Member level 4
Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ?
Is my coding approach too software-centric ?
Is my coding approach too software-centric ?
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mis-use of non-blocking assigns
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 `include "define.v" module check_data (clk, data_out, data_in, test_failed); // verifying the memory (circular buffer) read and write processes input clk; input [(`DATA_WIDTH-1) : 0] data_out; // memory output input [(`DATA_WIDTH-1) : 0] data_in; // memory input output reg test_failed = 0; wire data_out_is_valid; always @(posedge clk) begin if(((data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY) != (data_in + 1)) && data_out_is_valid) // due to "delay.v" test_failed <= 1; end assign data_out_is_valid = (data_in >= `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY) && (data_in < `MEMORY_SIZE + `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY); endmodule
Should I just split https://github.com/promach/internal_logic_analyzer/blob/master/rtl/check_data.v#L15 or the combinatorial logic at line 15 below across several registers ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 `include "define.v" module check_data (clk, data_out, data_in, test_failed); // verifying the memory (circular buffer) read and write processes input clk; input [(`DATA_WIDTH-1) : 0] data_out; // memory output input [(`DATA_WIDTH-1) : 0] data_in; // memory input output reg test_failed = 0; wire data_out_is_valid; always @(posedge clk) begin if(((data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY) != (data_in + 1)) && data_out_is_valid) // due to "delay.v" test_failed <= 1; end assign data_out_is_valid = (data_in >= `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY) && (data_in < `MEMORY_SIZE + `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY); endmodule
if (data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY) != (data_in + 1)) && data_out_is_valid)
the != compare will be true every time the RHS bitwise AND has a 0 on data_out_is_valid
Uh, I was assuming you have some background in logic design...was I wrong?Could you tell us more on this above statement ?
data_out_add != data_in_add && data_out_valid
The statement will only be false if data_out_add is exactly 0
I suppose inferred RAM coding is different across FPGA vendors, right ?
Can we infer dual port memories as RAM the same way on both Xilinx and Altera vendors ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 `include "define.v" module memory_block (clk, write_enable, waddr, raddr, data_write, data_read); input clk, write_enable; input [(`ADDR_WIDTH-1) : 0] waddr; input [(`ADDR_WIDTH-1) : 0] raddr; input [(`DATA_WIDTH-1) : 0] data_write; // data to be written into memory output reg [(`DATA_WIDTH-1) : 0] data_read; // data read out from memory reg [(`DATA_WIDTH-1) : 0] memory [(`MEMORY_SIZE-1) : 0]; always @(*) begin if (write_enable) memory[waddr] = data_write; end always @(*) begin if (!write_enable) data_read = memory[raddr]; end endmodule
Boy did I ever misread the code promach posted, I kept reading it as a bitwise AND instead of the logical AND operation.First, && is logical-and and binds weaker than !=.