shaiko
Advanced Member level 5
Hello,
I have a simple synchronous parallel bus that connects to the input pins of an FPGA.
The bus consists of the following signals:
1. Data (16 lines)
2. Valid
3. Clock
"Data" and "Valid" are synchronous to "Clock" which runs at 100MHz.
I want my FPGA to serialize the input and send it via an optical wire (SFP).
The receiving side of the fiber is also an. FPGA that does the opposite. I.E extract the clock and the signals synchronous to it.
The extracted clock on the receiving end will be driven into a PLL and used as a system clock.
Can you please suggest a SERDES In core that can connect to the SFP and can be implemented on a Xilinx device?
I have a simple synchronous parallel bus that connects to the input pins of an FPGA.
The bus consists of the following signals:
1. Data (16 lines)
2. Valid
3. Clock
"Data" and "Valid" are synchronous to "Clock" which runs at 100MHz.
I want my FPGA to serialize the input and send it via an optical wire (SFP).
The receiving side of the fiber is also an. FPGA that does the opposite. I.E extract the clock and the signals synchronous to it.
The extracted clock on the receiving end will be driven into a PLL and used as a system clock.
Can you please suggest a SERDES In core that can connect to the SFP and can be implemented on a Xilinx device?