Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Making GPIO pin of FPGA high.

Status
Not open for further replies.
H

hareeshP

Member level 3
Joined
Jul 19, 2017
Messages
59
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
491
Hi,
I am currently working on the the cyclone II FPGA and doing some simple programs. Now please anyone tell me how can i make a gpio pin of FPGA high through VHDL program and how to check whether the gpio is high or low.
 

just set it to '1'

gpio_pin <= '1';

and check it like any other signal:

Code: 
if gpio_pin = '1' then
  -- do something
 

VHDL is a hardware description language. I would stop thinking of it as a program, as it isn't executed by anything, it is synthesized into logic, i.e. FFs, gates, ram, etc.

A gpio pin is just a pin that can be used as an input or an output, when it is used as an output you need to set the output to the value you want and when used as an input you need to disable the output buffer with a tri-state control. To do this in VHDL looks something like this:

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

entity gpio_sig
port (
  gpio    : inout std_logic;
  dir     : in    std_logic   -- 0: in, 1: out
);
end entity;
 
architecture behav of gpio_sig is
  signal my_sig : std_logic;
begin
  -- output a 1 when dir is 1
  gpio <= 1'b1 when dir = '1' else 1'bz;
 
  -- can always read the gpio pin regardless of 0/1 dir.
  -- if dir is 0 then you'll read the external connection to the pin
  -- if dir is 1 you'll read whatever is being driven by the above logic.
  my_sig <= gpio;
 
end behave;
 

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10

library ieee;
use ieee.std_logic_1164.all;
entity gpio_fpga is
port(x, y: in std_logic;
       z: out std_logic);
end gpio_fpga;
architecture fpga_io of gpio_fpga is
begin
z<= x and y;
end fpga_io;


In the above program, if i assign x and y to a sliding switch and z to the gpio of fpga in the pin planner. Can i make the gpio high when the inputs x & y are high?
 

Now please anyone tell me how can i make a gpio pin of FPGA high through VHDL program and how to check whether the gpio is high or low.
Click to expand...

Connect the output signal z, to a FPGA pin that is connected to an on-board LED (study your development board guide, the pin connection info should be there if there are on-board LEDs). When x and y are both HIGH, then the LED should light up.
 

Hi,

it is not showing expected voltage.
Click to expand...
Maybe just your expectation is wrong.

Output level depends on:
* device type
* it's supply voltage
* load current
* output pin setup

Give use these informations and your expected voltage level, then we may verify this.

Klaus
 

hareeshP said:
But when i measure the voltage on the gpio pin after running the program, it is not showing expected voltage.
Click to expand...

When you synthesis a HDL file it generates the logical representation of the code.

When you go through place and route the tool tells the fpga what to do based on the synthesised file. Using the tool you can specify certain attributes of the FPGA IRRESPECTIVE of the vhdl.

These aspects are drive strength on pins etc.

You need to look at FPGA IO "constraints" and you will find the answers you're looking for.

- - - Updated - - -

hareeshP said:
But when i measure the voltage on the gpio pin after running the program, it is not showing expected voltage.
Click to expand...

When you synthesis a HDL file it generates the logical representation of the code.

When you go through place and route the tool tells the fpga what to do based on the synthesised file. Using the tool you can specify certain attributes of the FPGA IRRESPECTIVE of the vhdl.

These aspects are drive strength on pins etc.

You need to look at FPGA IO "constraints" and you will find the answers you're looking for.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top