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Multicast address in 10 Gig Ethernet IP

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Hi,
I already know what multicasting is: one sender several receivers.

I am trying to understand what should I do to opearte 10Gig IP core from Xilinx as multicast address.
https://www.xilinx.com/support/docu...n_gig_eth_mac/v15_0/pg072-ten-gig-eth-mac.pdf

in page 44, it is mentioned that:
"The least significant bit of the first octet of a MAC address determines if the address is an individual/unicast (0) or group/multicast (1) address. "

Any idea how to set this?
 

in page 44, it is mentioned that:
"The least significant bit of the first octet of a MAC address determines if the address is an individual/unicast (0) or group/multicast (1) address. "
Click to expand...

If you have a MAC address as DA 01 02 03 04 05, then it is a unicast address since the 1st octet which is DA, its LSB is 0 (DA = 1101 1010).
For multicast, just choose the LSB of the 1st octet to be 1.

Any idea how to set this?
Click to expand...
Have you taken a look at the eg_design simulation? In the TB somewhere they must be defining a 48bit constant and defining the MAC address. Find it and change it.
 

hi dpaul,
this is ovious but the thing is:
it is used in one of reference design from xilinx which I am using:
https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf

and in this reference design, this is what they used about MAC address in microblaze:

Code: 
#define EMAC1_BASEADDR 0x7C400000
#define EMAC2_BASEADDR 0x7C500000
#define FAULTINHIBIT_OFFSET_REG 0x410
#define MAC_FAULT_BITS 0x30000000
#define FI_BIT 0x08000000
#define FI_BIT_MASK 0xF7FFFFFF
void toggle_EMAC_fault_inhibit(void)
{
int reconciliation_reg = 0;
reconciliation_reg = Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG);
if (reconciliation_reg & FI_BIT){
FI = 0;
xil_printf("\r\nFault Inhibit: Disabled\r\n");
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg & FI_BIT_MASK);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg & FI_BIT_MASK);
}
else{
FI = 1;
xil_printf("\r\nFault Inhibit: Enabled\r\n");
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg | FI_BIT);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg | FI_BIT);
}
}
void Enable_EMAC_fault_inhibit(void)
{
do{
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG) | FI_BIT);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, Xil_In32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG) | FI_BIT);
} while (((Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG) & Xil_In32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG))&FI_BIT_MASK) == 0);
}

and I didn't understand what need to be changed here for this purpose.
 

In this doc https://www.xilinx.com/support/docum...56-over-ip.pdf, as I see it, in Table 5 some stuff need to be set. The first 4 MAC address there (Primary and Sec) are unicast addresses. You have to change these values via s/w I guess, to set your multicast address.

Understand the s/w flow, what it does at each step, and then change it accordingly.
 

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