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Floating Signal in Multi voltage design or low power

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a2vlsi

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If my signal coming into ON domain is floating (not isolate by isolator), then what probable issue seems to be as per low power concept.
 

Without fully understanding what you are doing, I would assume the signal will eventually be routed to a CMOS gate. So you will have a transistor with a floating input gate. It will not work reliably.
 

If you mentioned, I think leakage power will occur on the floating gate (in ON domain).

On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur.
 

hyun5226 said:
If you mentioned, I think leakage power will occur on the floating gate (in ON domain).

On floating gate, Because It is possible to propagate X signal (neither 0 nor 1), leakage will occur.
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leakage is the least of your concerns. the design will not work.
 

ThisIsNotSam said:
leakage is the least of your concerns. the design will not work.
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During synthesis we always have floating signal and design will work.
crowbar or shot circuit current is the perfect concern.

Please correct me, if I am wrong.
 

a2vlsi said:
During synthesis we always have floating signal and design will work.
crowbar or shot circuit current is the perfect concern.

Please correct me, if I am wrong.
Click to expand...

You are very wrong. Simulate a CMOS inverter. Let the input gate floating. See what you get.

Synthesis is about design manipulation. It cares very little if signals are connected or to where. The actual silicon would not work, 100% guaranteed.
 

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