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[moved] Uncertainty on generated clock and extra margin

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mepriyasingh

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1. What will be the uncertainty value at the generated clock, will it remain same or more than the master.
2. What is the exact significance in "extra margin" in set_clock_uncertainty" (fairly confusing)?
 

these terms are always vague. uncertainty, to me, in a physical synthesis context, means variation in the external clock source.

1) same, but often actual timing is worse because of min/max variation on the clock path that is longer than the master by at least a few gates
2) I think you are hinting at a safety margin that most designers will add on their own. a few picoseconds here and there to account for some modelling inaccuracy.
 
2) I think this "Extra margin" might be more than "safety margin".
 

mepriyasingh said:
2) I think this "Extra margin" might be more than "safety margin".
Click to expand...

where exactly are you getting this extra margin from? my tool of choice says the following about the command:
set_clock_uncertainty uncertainty_value [-setup] [-hold] [-rise | -fall] { {-from | -rise_from | -fall_from} clksig_from_list {-to | -rise_to | -fall_to} clksig_to_list | pin_or_clock_list }
Click to expand...
 

My "Extra margin" term concern with:
uncertainty_value = skew + jitter + "Extra margin".
 

mepriyasingh said:
My "Extra margin" term concern with:
uncertainty_value = skew + jitter + "Extra margin".
Click to expand...

Probably makes sense in a synthesis context ; 'extra margin' might help downstream stages like CTS/PnR to meet timing with less effort.

- - - Updated - - -

ThisIsNotSam said:
these terms are always vague. uncertainty, to me, in a physical synthesis context, means variation in the external clock source.

1) same, but often actual timing is worse because of min/max variation on the clock path that is longer than the master by at least a few gates
2) I think you are hinting at a safety margin that most designers will add on their own. a few picoseconds here and there to account for some modelling inaccuracy.
Click to expand...

In case of 1) wouldn't the rise-to-rise uncertainty become 2x when you have div-by-2 clock ?
 

harpv said:
Probably makes sense in a synthesis context ; 'extra margin' might help downstream stages like CTS/PnR to meet timing with less effort.

- - - Updated - - -



In case of 1) wouldn't the rise-to-rise uncertainty become 2x when you have div-by-2 clock ?
Click to expand...

No, it is proportional to the clock path length, not the division factor.
 

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