Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

negative WNS for clock gating path

Status
Not open for further replies.
R

r1caw ex ua6bqg

Member level 2
Joined
Jun 27, 2017
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
403
Hi all!
I am a student studying digital design in the university.
I have a question about Synopsys IC Compiler commands which can help reduce negative setup slack in the clock gate path. I know that this situation because of late arrival of launch clock (i.e. clock skew) in comparison with capture (for clock gate) - launch clock delay is more than capture clock delays.
So, how I can solve this problem? May be there is some commands for ICC compiler?

Thank you!
 

late arrival vs early arrival is usually taken care at the clock tree step, and it should be transparent whether any of the individual clock signals are gated or not.

the fix is to get timing to pass. take a look at your clock tree targets and at your overall clock period.
 

Thank you for your answer!
Do you mean that during CTS all clocks will be treated as clocks without clock gated cells, and ICC optimizes skew like there is no clock gated cells inside the clock tree?

In my timing report after CTS I can see that clock network delay for launch is 0.43 and clock network delay for capture is 0.16. But report_clock_tree gives me clock skew 0.13 (for the same scenario). Why there is difference?
 

ua6bqg said:
Thank you for your answer!
Do you mean that during CTS all clocks will be treated as clocks without clock gated cells, and ICC optimizes skew like there is no clock gated cells inside the clock tree?

In my timing report after CTS I can see that clock network delay for launch is 0.43 and clock network delay for capture is 0.16. But report_clock_tree gives me clock skew 0.13 (for the same scenario). Why there is difference?
Click to expand...

you need to do some reading on clock trees. from CTS point of view, doesn't matter if the endpoint is a flop, a clock gating cell, a macro. it will balance and skew all of them as needed.

I don't use ICC so I can't tell you what the report_clock_tree command does differently.
 
Thank you!
Do you mean that I need read more about CTS and clock trees or set a command to ICC to observe clock trees?
 

read more about CTS process in general.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top