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Design D Flip Flop at 40Gbps

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KimPhan

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Hi everyone,
I need to design DFF at 40Gbps with high performance.
How can I do this? I search some article but it's performance is really not good.
Everybody knows it please help me.
Thank you so much.:thumbsup:
 

Which production process (structure size) do you have in mind? Supply voltage? Load impedance?
 

erikl said:
Which production process (structure size) do you have in mind? Supply voltage? Load impedance?
Click to expand...

Supply voltage is 2V, Data is 40Gbps and Clk is 10Gbps. I use the CMOS TSMC 130nm technology.
Thank for your help.:thumbsup::thumbsup::thumbsup:
 

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