Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] What type is this component instantiation code bram, dram , fifo or what ?

Status
Not open for further replies.
A

abimann

Member level 4
Joined
Jun 21, 2016
Messages
77
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
673
What type is this component instantian code bram, dram , fifo or what ?

This DaveShahs code for MIPI, I am doing customization for OV4689 and I cannot understand how to do buffer, I thought it BRAM and when i try i cannot to make it because for bram addresses must be same width but here is different address A , Address B, Data in and Data out.
Please someone explain how to do this different input and output for same buffer . Or this is not bram ? 

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

COMPONENT input_line_buffer
    PORT (
      clka : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
      dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
      clkb : IN STD_LOGIC;
      addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)
    );
  END COMPONENT;
 
  COMPONENT output_line_buffer
    PORT (
      clka : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
      clkb : IN STD_LOGIC;
      addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
    );
  END COMPONENT;
 
Last edited by a moderator:

Re: What type is this component instantian code bram, dram , fifo or what ?

You've got input data 64 bits wide and 4096 deep. That's 256K bits. Output is 256 bits wide and 1024 deep. Also 256K bits. It's simply mapping the address space differently. For example, when you read address 0, you read the first FOUR data words that were written.

- - - Updated - - -

Btw, your comment "bram addresses must be same width" is false and apparently the source of your confusion.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top