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What are the subsitutes for tranif0,tranif1 and rtran constructs in Tetramax ATPG too

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kaushikrvs

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The Tetramax ATPG tool doesn't understand tranif1 , tranif0 , and rtran constructs?

However , I found a substitute for bufif1 as _TSD (ATPG Tetramax) and it works. I need a similar substitute for tranif1 , tranif0 , rtran.
 

kaushikrvs said:
The Tetramax ATPG tool doesn't understand tranif1 , tranif0 , and rtran constructs?

However , I found a substitute for bufif1 as _TSD (ATPG Tetramax) and it works. I need a similar substitute for tranif1 , tranif0 , rtran.
Click to expand...

why would you need the test tool to understand these primitives? what are you trying to do exactly?
 

Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
 

kaushikrvs said:
Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
Click to expand...

and you don't see anything wrong with that?
 

I don't see anything such , even though my block is wrong , My question is plain and simple, Are there any constructs in Tetramax that can be substituted in place of tranif0 and tranif1?
 

You cannot substitute r/tran/0/1 primitives with buf/1/0 or anything else without knowing the context of their usage. All of the tran primitives provide bi-directional flow of signals
 

Verilog models for tranif 1 and tranif0

How to write Verilog model for tranif1 and tranif0 ?
 

Re: Verilog models for tranif 1 and tranif0

Rightly said in #2.

tranif1 - Bi-directional transistor (High)
tranif0 - Bi-directional transistor (Low)

You use Verilog/VHDL for RTL modeling. You cannot model below gates with Verilog/VHDL.
 

Re: Verilog models for tranif 1 and tranif0

It is not possible to model the full behavior of a tranif1/0 primitive within the Verilog language itself. And I'm not sure if the VPI gives you the capability to resolve the wires involved in C code. And even if you could, that would not solve the problem you mention in your previous post - the down stream tool would not recognize the C code you wrote.

What you need to do is look at the larger context and try to replace the functionality around it.
 

I wondering if it is being overlooked that the OP has a synthesized placed and routed module and an unsynthesized RTL module.
kaushikrvs said:
Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
Click to expand...

Is seems to me the problem is they should have synthesized the RTL module so that it has the correct library primitives instead of using the RTL directly along with the placed and routed netlist module. But perhaps this is not the way the tools work now days.
 

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