aditmohan96
Newbie level 1
Hi all,
I generated the following STIL file after path delay fault atpg in tetramax. its a combinational circuit with input and output latches. I don't understand why there are 4 vectors for each pattern. Also I what does the capture-clk and capture procedures do? I'm having trouble with the syntax (I'm a noob).
I generated the following STIL file after path delay fault atpg in tetramax. its a combinational circuit with input and output latches. I don't understand why there are 4 vectors for each pattern. Also I what does the capture-clk and capture procedures do? I'm having trouble with the syntax (I'm a noob).
Code:
STIL 1.0;
Header {
Title " TetraMAX(R) K-2015.06-SP5-2-i160411_145730 STIL output";
Date "Mon Jun 12 21:01:22 2017";
History {
Ann {* Collapsed Path_delay Fault Summary Report *}
Ann {* ----------------------------------------------- *}
Ann {* fault class code #faults *}
Ann {* ------------------------------ ---- --------- *}
Ann {* Detected DT 9 *}
Ann {* Possibly detected PT 0 *}
Ann {* Undetectable UD 0 *}
Ann {* ATPG untestable AU 0 *}
Ann {* Not detected ND 0 *}
Ann {* ----------------------------------------------- *}
Ann {* total faults 9 *}
Ann {* test coverage 100.00% *}
Ann {* ATPG effectiveness 100.00% *}
Ann {* ----------------------------------------------- *}
Ann {* *}
Ann {* Pattern Summary Report *}
Ann {* ----------------------------------------------- *}
Ann {* #internal patterns 5 *}
Ann {* #fast_sequential patterns 5 *}
Ann {* ----------------------------------------------- *}
Ann {* *}
Ann {* rule severity #fails description *}
Ann {* ---- -------- ------ --------------------------------- *}
Ann {* B10 warning 4 unconnected module internal net *}
Ann {* P7 warning 9 capture earlier than path cycle time *}
Ann {* P26 warning 18 signal missing pulsed waveform in waveformtable *}
Ann {* *}
Ann {* clock_name off usage *}
Ann {* ---------------- --- -------------------------- *}
Ann {* clk 0 nonscan_DFF *}
Ann {* *}
Ann {* There are no constraint ports *}
Ann {* There are no equivalent pins *}
Ann {* There are no net connections *}
Ann {* top_module_name = c17 *}
}
}
Signals {
"n1" In; "n2" In; "n3" In; "n6" In; "n7" In; "clk" In; "n22" Out; "n23" Out;
}
SignalGroups {
"_pi" = '"n1" + "n2" + "n3" + "n6" + "n7" + "clk"'; // #signals=6
"_in" = '"n1" + "n2" + "n3" + "n6" + "n7" + "clk"'; // #signals=6
"_po" = '"n22" + "n23"'; // #signals=2
"_out" = '"n22" + "n23"'; // #signals=2
"_default_In_Timing_" = '"n1" + "n2" + "n3" + "n6" + "n7" + "clk"'; // #signals=6
"_default_Out_Timing_" = '"n22" + "n23"'; // #signals=2
"_default_Clk0_Timing_" = '"clk"'; // #signals=1
}
Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
Waveforms {
"_default_In_Timing_" { 0 { '0ns' D; } }
"_default_In_Timing_" { 1 { '0ns' U; } }
"_default_In_Timing_" { Z { '0ns' Z; } }
"_default_In_Timing_" { N { '0ns' N; } }
"_default_Clk0_Timing_" { P { '0ns' D; '50ns' U; '80ns' D; } }
"_default_Out_Timing_" { X { '0ns' X; } }
"_default_Out_Timing_" { H { '0ns' X; '40ns' H; } }
"_default_Out_Timing_" { T { '0ns' X; '40ns' T; } }
"_default_Out_Timing_" { L { '0ns' X; '40ns' L; } }
}
}
}
UserKeywords ScanChainGroups;
ScanStructures {
// Uncomment and modify the following to suit your design
// ScanChain "chain_name" { ScanIn "chain_input_name"; ScanOut "chain_output_name"; }
}
PatternBurst "_burst_" {
PatList { "_pattern_" {
}
}}
PatternExec {
PatternBurst "_burst_";
}
UserKeywords ActiveScanChains;
Procedures {
"capture_clk" {
W "_default_WFT_";
C { "_po"=XX; }
"forcePI": V { "_pi"=######; }
"measurePO": V { "_po"=##; }
C { "_po"=XX; }
"pulse": V { "clk"=P; }
}
"capture" {
W "_default_WFT_";
C { "_po"=XX; }
"forcePI": V { "_pi"=######; }
"measurePO": V { "_po"=##; }
}
// Uncomment and modify the following to suit your design
// load_unload {
// V { "clk" = 0; } // force clocks off and scan enable pins active
// Shift { V { _si=#; _so=#; "clk" = P; }} // pulse shift clocks
// }
}
MacroDefs {
"test_setup" {
W "_default_WFT_";
V { "clk"=0; }
}
}
Pattern "_pattern_" {
W "_default_WFT_";
"precondition all Signals": C { "_pi"=000000; "_po"=XX; }
Macro "test_setup";
Ann {* fast_sequential *}
"pattern 0": Call "capture_clk" {
"_pi"=011100; }
Call "capture_clk" {
"_pi"=010110; }
Call "capture_clk" {
"_pi"=000110; }
Call "capture" {
"_pi"=001000; "_po"=HH; }
Ann {* fast_sequential *}
"pattern 1": Call "capture_clk" {
"_pi"=011100; }
Call "capture_clk" {
"_pi"=111010; }
Call "capture_clk" {
"_pi"=011110; }
Call "capture" {
"_pi"=110000; "_po"=HH; }
Ann {* fast_sequential *}
"pattern 2": Call "capture_clk" {
"_pi"=001110; }
Call "capture_clk" {
"_pi"=011000; }
Call "capture_clk" {
"_pi"=010110; }
Call "capture" {
"_pi"=101000; "_po"=HH; }
Ann {* fast_sequential *}
"pattern 3": Call "capture_clk" {
"_pi"=000010; }
Call "capture_clk" {
"_pi"=101110; }
Call "capture_clk" {
"_pi"=110000; }
Call "capture" {
"_pi"=100010; "_po"=HL; }
Ann {* fast_sequential *}
"pattern 4": Call "capture_clk" {
"_pi"=101100; }
Call "capture_clk" {
"_pi"=000010; }
Call "capture_clk" {
"_pi"=101110; }
Call "capture" {
"_pi"=111010; "_po"=LH; }
}
// Patterns reference 56 V statements, generating 56 test cycles