hcu
Advanced Member level 4
creating axi slave peripheral in vivado ?
Hello all,
I have a verilog design with a port list of
input clk_100Mhz,
input clk_50Mhz,
input rst,
input [7:0] DATA_P,
input control,
output [15:0] DATA_Q. I want to create axi slave peripheral. BTW I'm on Vivado.
I brought out a axi slave peripheral template in vivado with the options available. I instantiated my design just.
and now tell me how to port map my design signals with axi slave signals. I know very little about axi protocol.
Hello all,
I have a verilog design with a port list of
input clk_100Mhz,
input clk_50Mhz,
input rst,
input [7:0] DATA_P,
input control,
output [15:0] DATA_Q. I want to create axi slave peripheral. BTW I'm on Vivado.
I brought out a axi slave peripheral template in vivado with the options available. I instantiated my design just.
and now tell me how to port map my design signals with axi slave signals. I know very little about axi protocol.