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DRC Violations in Encounter

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inputoutput

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After running nanoroute in Encounter I get the following message

WARNING (NRDR-30) Detail routing is stopped because of too many drc violations
Click to expand...

#Total number of DRC violations = 1062773
#Total number of violations on LAYER M1 = 68363
#Total number of violations on LAYER M2 = 241961
#Total number of violations on LAYER M3 = 155041
#Total number of violations on LAYER M4 = 191680
#Total number of violations on LAYER M5 = 263796
#Total number of violations on LAYER M6 = 34971
#Total number of violations on LAYER M7 = 106961
Click to expand...

The violations are due to spacing. During route I get the following warning, I don't know if it's a reason for the problem

#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000
#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.
Click to expand...

I have done place and route for other designs using this same library without much problems. I don't think it's a congestion issue, as the density is only 30% or thereabouts.
Where to begin to solve this problem?
 

So many things could be wrong. I assume you are using nanorouter, correct? And it looks like the tech lef wasn't loaded correctly?
 

ThisIsNotSam said:
So many things could be wrong. I assume you are using nanorouter, correct? And it looks like the tech lef wasn't loaded correctly?
Click to expand...

Yes, the errors occur after nanoroute. But I now notice that the violations started after CTS. There are no violations after placement. Any ideas why CTS could be causing violations?
 

Did CTS start real routing of clock nets?
 

inputoutput said:
Yes, the errors occur after nanoroute. But I now notice that the violations started after CTS. There are no violations after placement. Any ideas why CTS could be causing violations?
Click to expand...

placement does no real routing, only a mock trial route. placement will never fail because of 'routing'

I bet your CTS is routing the clock tree already. that is one net and one net only, and you are already getting thousands of drcs. something is clearly wrong.
 

These violations are reported after CTS. Any idea what they could mean? Where do I begin?

AREA: Regular Via of Net n810370 ( M2 )
Bounds : ( 1533.150, 344.710 ) ( 1533.250, 344.925 )
Actual: 0.0215 Min: 0.052

SHORT: Regular Via of Net n693130 & Regular Wire of Net n693290 ( M2 )
Bounds : ( 1527.550, 344.745 ) ( 1527.650, 344.925 )

NSMETAL: Regular Via of Net n701454 & Pin of Cell U515857 ( M1 )
Bounds : ( 1327.110, 344.890 ) ( 1327.160, 344.940 )
Actual: 0.07 Min: 0.09


MINSTEP: Regular Via of Net n698007 & Pin of Cell U704261 ( M1 )
Bounds : ( 1436.045, 343.250 ) ( 1436.110, 343.300 )
Actual: 0.065 Min: 0.09
Click to expand...

There are more than 1000 of these violations.
 

inputoutput said:
These violations are reported after CTS. Any idea what they could mean? Where do I begin?



There are more than 1000 of these violations.
Click to expand...

There is always a pattern. You have to find it.
 

How are you checking the DRC errors? You can output a list that shows what kinds of DRC violations. Do that and post it here. Its under "verify geometry".
 

mwb said:
How are you checking the DRC errors? You can output a list that shows what kinds of DRC violations. Do that and post it here. Its under "verify geometry".
Click to expand...

Depends on tool version and technology being used. They should be in the violation browser, but the way to get them there changes from verify_geometry to verify_drc
 

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