houjiali
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I have designed a 12 bit SAR ADC with CDAC. There are a 4-bit MSB section and a 8bit LSB section in the CDAC. The architecture of comparator is 3-stage pre-amplifier+latch,whose VCM is generated by a resistor ladder. The spec is 125sps(2Mhz CLK) .
I tested the chip with input of 1.1kHz and 1Mhz clk. The DNL in 1/4FS 1/2FS 3/4FS is quite high.
**broken link removed**
**broken link removed**
I tested the chip with input of 1.1kHz and 1Mhz clk. The DNL in 1/4FS 1/2FS 3/4FS is quite high.
**broken link removed**
**broken link removed**