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Problem in Verilog Array

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manik045

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Hello

I have the following code in Modelsim 10.1b.

Code: 
module TwoD_Array ();
  
  reg  array [3:0] [7:0]; //={1010, 1110, 1111,1011};
  
 initial begin
   
   array [0][1]=11001101; //{{11001101}|{11110101}|{10101111}|{11100111}};
   //array = '{{8'b0},{8'b1},{8'b0},{8'b1}};
//$display ("array[0][0]= %b", array[0][0]);
$display ("array [0][1]=%b", array[0][1]);
end 
endmodule

I have the following output.

# array [0][1]=1

Why it's happening? Here should be 11001101. I do not understand. Please help to input the values in the 2D array. I know that verilog does not support packed array. But if i want to put multiple values at a time in verilog what should i do?

Any help regarding this issue very helpful. Please give an example of related fault.

Thanks in advance.
 

If you are being restricted to using Verilog, not SystemVerilog, you can only access one bit at a time. The only way to make an assignment to a 2D unpacked array is to nested for-loop. Maybe you meant to declare your array as

Code: 
reg [7:0] array [3:0];

array[0] = 8'11001101;
 
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