TonyLS
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I am synthesizing with boundary optimization set. The RTL to Netlist formality run has 32 failures. All from the same 32 bit bus. During debug I noticed there is an inversion (additional inverter in the netlist) in the cone of logic going into the flop that is failing. All 32 register Q outputs connect to the output of the module. I take it DC performed boundary optimization and pushed an inverter into the cone of logic instead of outside the module.
I removed boundary optimization and re-synthesized. The RTL to Netlist formality run now passes.
compile_ultra switches for failing run:
-spg -no_auto_layer_optimization -scan -no_autoungroup -no_seq_output_inversion -gate_clock
compile_ultra switches for passing run:
-spg -no_auto_layer_optimization -scan -no_autoungroup -no_seq_output_inversion -gate_clock -no_boundary_optimization
So my questions are:
- Shouldn't DC provide information within the SVF guidance file about any boundary optimization it decides to do? If so what should I be looking for in the svf?
- Is there something I am missing to have a successful formality run and keep boundary optimization turned on in synthesis? The area is very much improved with boundary opt on.
Any feedback is appreciated.
I removed boundary optimization and re-synthesized. The RTL to Netlist formality run now passes.
compile_ultra switches for failing run:
-spg -no_auto_layer_optimization -scan -no_autoungroup -no_seq_output_inversion -gate_clock
compile_ultra switches for passing run:
-spg -no_auto_layer_optimization -scan -no_autoungroup -no_seq_output_inversion -gate_clock -no_boundary_optimization
So my questions are:
- Shouldn't DC provide information within the SVF guidance file about any boundary optimization it decides to do? If so what should I be looking for in the svf?
- Is there something I am missing to have a successful formality run and keep boundary optimization turned on in synthesis? The area is very much improved with boundary opt on.
Any feedback is appreciated.