help in customizable PTM models

Hello all,

I'm trying to use the Nano-CMOS customizable model generator (URL:http://ptm.asu.edu/) to generate 45nm NMOS and PMOS transistor models with 0.1V threshold voltage. However, when I specify Vth=0.1V (and keep all other variables as default), I get this graph (see attached picture) which shows Vth way far from 0.1V and when I open nominal model I find Vth0=0.411



If someone used this generator before, I have some simple questions:
1) In attached picture, Vth has two input bars...does the second bar defines the undefined region between high and low...or they're just two ways of inputs (one for volts and one for milli-volts) ?
2) Can I decrease threshold voltage to any value or there is a minimum value ?
3) Can anyone tell me/give me some references to know how these variables affect threshold voltage, setup and hold time of transistors ?

oAwad said:

Hello all,

I'm trying to use the Nano-CMOS customizable model generator (URL:http://ptm.asu.edu/) to generate 45nm NMOS and PMOS transistor models with 0.1V threshold voltage. However, when I specify Vth=0.1V (and keep all other variables as default), I get this graph (see attached picture) which shows Vth way far from 0.1V and when I open nominal model I find Vth0=0.411

View attachment 137961

If someone used this generator before, I have some simple questions:
1) In attached picture, Vth has two input bars...does the second bar defines the undefined region between high and low...or they're just two ways of inputs (one for volts and one for milli-volts) ?
2) Can I decrease threshold voltage to any value or there is a minimum value ?
3) Can anyone tell me/give me some references to know how these variables affect threshold voltage, setup and hold time of transistors ?

Click to expand...

1) I don't see any bars.
2) 0.1V and 17nm effective L for a 45nm tech doesn't sound wise. I doubt the model can work accurately for this scenario. How are you picking these values?
3) transistors don't have setup/hold time. you need a cell for that.

ThisIsNotSam said:

1) I don't see any bars.
2) 0.1V and 17nm effective L for a 45nm tech doesn't sound wise. I doubt the model can work accurately for this scenario. How are you picking these values?
3) transistors don't have setup/hold time. you need a cell for that.

Click to expand...

Sorry if I was not clear. By input bars I mean the two input boxes in front of Vth. They didn't provide any instructions for this online tool so I'm not really sure about there usage. My intention is to create a 45nm NMOS & PMOS model with Vth=0.1V for some simulations and there's no fabrication constraints, so if I decreased Leff will it help ?
and can you suggest values for such a model ? (Vdd = 1.1V)

- - - Updated - - -

and regarding setup/hold time of a logic cell (ex. DFF)...is the definition of setup/hold time is that input should be constant during this time or generally greater than cell threshold voltage ? (so maybe varying but still above cell threshold) in case of logic 1