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[SOLVED] Gate level simulation in Xilinx ISE

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oAwad

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Hello all,

Can I simulate my gate level netlist + sdf timing files (generated by Design Compiler) in Xilinx ISE ? How to include the sdf file in Xilinx ISE ? (since this is the only logic simulator I have)

I have searched online but couldn't find a way to include sdf from another tool to do timing simulation so maybe someone here can help.
 

Are you saying the sdfanno command in isim won't accept the SDF generated by DC? Maybe you need to write out the SDF V2.1 format. You'll also have to compile the entire ASIC design library of all your cells so the gate level netlist can be simulated.

ISIM is a really slow simulator, you might be better off downloading icarus for this.
 

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