monglebest
Junior Member level 1
Hi, all:
I am taking the course of RF CMOS IC Design and realized that normal on-die inductor can give a Q around 4 due large ESR. If I am going to have a 2.4GHz carrier signal, then based on the definition of Q.
Q=fc/BW=>BW=fc/Q=2.4G/4=600MHz.
This 3dB BW seems unreasonable large for me. I would expect a 3dB BW around 100KHz or 10KHz.
I have this assumption because normal PLL/CDR BW is around 1MHz or 10MHz. To effectively suppress the oscillator phase noise, the oscillator 3dB BW should much smaller than PLL/CDR BW. I get this conclusion from a Lorenzian shape phase noise model in optical communication. Please correct me where do I get wrong.
What's the application for a VCO with Q=4? How does the RF IC design made nowadays? I remember that I see a GPS chip has a Q over 10,000. How is that large Q achieved?
I am taking the course of RF CMOS IC Design and realized that normal on-die inductor can give a Q around 4 due large ESR. If I am going to have a 2.4GHz carrier signal, then based on the definition of Q.
Q=fc/BW=>BW=fc/Q=2.4G/4=600MHz.
This 3dB BW seems unreasonable large for me. I would expect a 3dB BW around 100KHz or 10KHz.
I have this assumption because normal PLL/CDR BW is around 1MHz or 10MHz. To effectively suppress the oscillator phase noise, the oscillator 3dB BW should much smaller than PLL/CDR BW. I get this conclusion from a Lorenzian shape phase noise model in optical communication. Please correct me where do I get wrong.
What's the application for a VCO with Q=4? How does the RF IC design made nowadays? I remember that I see a GPS chip has a Q over 10,000. How is that large Q achieved?