oAwad
Full Member level 2
Hello,
I have a layout design in SoC encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell Library.
I'm beginning my design using LEF files.
My questions are:
- Can I do this modification in SoC encounter or I have to go for Virtuoso ?
- If Virtuoso, what is the best format to export my design (GDS or OA) ? and how ? (Please provide detailed description)
- I want to know if there is a difference between parasitic extraction in Virtuoso and encounter. (Which is better in analyzing coupling capacitance between interconnect wires) ?
Thanks
I have a layout design in SoC encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell Library.
I'm beginning my design using LEF files.
My questions are:
- Can I do this modification in SoC encounter or I have to go for Virtuoso ?
- If Virtuoso, what is the best format to export my design (GDS or OA) ? and how ? (Please provide detailed description)
- I want to know if there is a difference between parasitic extraction in Virtuoso and encounter. (Which is better in analyzing coupling capacitance between interconnect wires) ?
Thanks