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Output valid delay timing and maximum float delay time

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Hi i was going through i486SX processor datasheet,

They are specifying terms like Output Valid delay timing and Maximum Float delay timing.
Im new to microprocessor/FPGA/CPLD designs.

I just wanted to know what exactly these terms mean?
Im just writing below that it might mean..can some body please clarify?

Output Valid delay-Your output will be valid after the CLK edge after the specified time?
Float Delay- The bus will return /released to float state after the CLK edge after the specified time?

How this will be impacting in the design? Will it create signal integrity issues?

Thanks for any help,


outvalid.JPGfloatdelay.JPG
 

Output Valid delay-Your output will be valid after the CLK edge after the specified time?
Click to expand...
Correct, also known as "output delay".

Regarding the "float delay" - looks like it's the required "hold time". I.E : the minimum time that the data remains valid after a clock edge.

How this will be impacting in the design? Will it create signal integrity issues?
Click to expand...
These are the timing requirements of the digital circuit - You simply have to ensure that there're properly met.
Failing to meet them may cause - "data integrity" problems (incorrect sample data)

It has nothing to do with "signal integrity". Although "signal integrity" issues can definitely cause timing problems.
 

Thanks for the support.. I came to know that float delay can also be critical, in case of interactions with peripharals and can cause bus contention. slow/fast peripherals may try to access the bus slow/fast compared to the processor read/write may cause errors if not properly designed.

Regards
 

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