ISE 14.6 - Design to large for FPGA - Still generates bit file

Hello everyone!

I'm working on a design using ISE 14.6 and there is something that I don't really understand that ISE is doing. When I start the operation to generate the programming file I get a warning that says the design is too big for the FPGA and when I look in the design results tab the percentage of LUTs used is 118%. Which is fine but it is only like this during the synthensize phase. ISE then happily continues with the last phases and generates a programming file. Then when I look at the design results tab everything is now under 100% but some are very close.

Does ISE just prune the design so that it fits? I tried using the file but it didn't seem to work(unsurprisingly).

What is going on here?

Also while I'm on the subject I also get this warning:
I take this means the design is too large but where is the 153 coming from? Is it suggesting that the design 153% of the available resources? The highest number I can find in the report is 118%.

Thank you!

pigtwo said:

Hello everyone!

I'm working on a design using ISE 14.6 and there is something that I don't really understand that ISE is doing. When I start the operation to generate the programming file I get a warning that says the design is too big for the FPGA and when I look in the design results tab the percentage of LUTs used is 118%. Which is fine but it is only like this during the synthensize phase. ISE then happily continues with the last phases and generates a programming file. Then when I look at the design results tab everything is now under 100% but some are very close.

Does ISE just prune the design so that it fits? I tried using the file but it didn't seem to work(unsurprisingly).

What is going on here?

Click to expand...

ISE map does transformations on the logic to pack the design into LUTs, it will also remove any unused logic or logic that is deemed to be a constant. Once all that is done it might actually fit the device selected. It's likely not going to meet timing though, so I suspect you have timing violations (perhaps didn't even supply timing constraints) or your design doesn't actually work as you didn't run any functional simulations on the HDL code. The other possibility (which is an intermittent bug) is if you enabled -opt_design in map (I think) and it attempts to do some optimizations on the logic, which inadvertently changes the functionality of the design. I was told by the FAE (who was told by the factory, the ISE software engineers) that you shouldn't use that option as they've never found out why some designs fail after turning that feature on.

pigtwo said:

Also while I'm on the subject I also get this warning:

Code:

WARNING:Xst:2254 - Area constraint could not be met for block <LED_Grid>, final ratio is 153.

I take this means the design is too large but where is the 153 coming from? Is it suggesting that the design 153% of the available resources? The highest number I can find in the report is 118%.

Thank you!

Click to expand...

I think that means the area constraint you supplied for the LED_Grid block was using 153% of the resources that were given for the area constraint you supplied. It means you have an area constraint that was too small. I would nix all the area constraints you've added to your UCF file. From what I seen with others using them, unless you know exactly what you are doing they generally will hinder the implementation tools instead of helping. I use them very sparingly and only on stuff I know should be placed a certain way to improve timing (and the tools refuse to place them correctly).

Ah ok, I'm not super familiar with what step does what. I thought that the synthensizer phase also optimized, so that makes sense. I did simulate and it didn't seem to have problems but I didn't finish verifying when I saw that warning. It is likely that there is something wrong with the design.

As you guessed I didn't supply timing constraints. Timing constraints and meeting timing is something I know very little about. Maybe because I generally don't use very high frequencies I've gotten away with it but I do desperately need to learn about this.

Thank you again!