kasarayv
Newbie level 3
I am having issues with my design when performing synthesis in Quartus II. The synthesis gives me these two warnings:
The first warning includes all the outputs of the top-level module. And the second warning includes all the inputs of the top-level module. I have assigned all the input/output pins in the Pin Planner(so as not to leave any pins hanging). I am still unable to get rid of these warnings. And due to these warnings the synthesis generates 0 logic elements. I completed the entire compilation process (despite these warnings) and have run an RTL simulation with a testbench that I wrote and the simulation seems to work perfectly. However, as I assume the design is not synthesizing correctly.
Please help me rectify any issues in my code.
Thanks
Warning (13024): Output pins are stuck at VCC or GND
Warning (21074): Design contains 203 input pin(s) that do not drive logic
The first warning includes all the outputs of the top-level module. And the second warning includes all the inputs of the top-level module. I have assigned all the input/output pins in the Pin Planner(so as not to leave any pins hanging). I am still unable to get rid of these warnings. And due to these warnings the synthesis generates 0 logic elements. I completed the entire compilation process (despite these warnings) and have run an RTL simulation with a testbench that I wrote and the simulation seems to work perfectly. However, as I assume the design is not synthesizing correctly.
Please help me rectify any issues in my code.
Thanks