Ahmed Hisham
Newbie level 3
Code:
module aaa(input logic a,b,c,output logic y);
assign y=~a&~b&~c | a&~b&~c | a&~b&c;
endmodule
i am using Quartus for simultion at the begining of the creation of the project i chosed verilog
as there is no for system verilog
now this error is given to me for the code a
Error (10161): Verilog HDL error at aaa.v(2): object "logic" is not declared