harry998
Newbie level 3
Hi guys ive been playin around with altera fpga's for a while and managed a few basic projects but im struggling with this one and none of the books and tutorials ive got seem to help (i think it might be a timing issues)
The code is for a very basic spi master that esseential just transmits a 1 byte instruction in spi protocol.
The count register keeps track of how many spi clocks have gone past and should output a high bit on clock 7 and 8 at the minute i get a high clock output at (approx because i dont have my scope with me) the 15th clock falling edge.
* note its a repeating signal every 15 ish clocks not just a one shot
Is this a timing issue or am i doing something obviously silly? :-S
The code is for a very basic spi master that esseential just transmits a 1 byte instruction in spi protocol.
The count register keeps track of how many spi clocks have gone past and should output a high bit on clock 7 and 8 at the minute i get a high clock output at (approx because i dont have my scope with me) the 15th clock falling edge.
* note its a repeating signal every 15 ish clocks not just a one shot
Is this a timing issue or am i doing something obviously silly? :-S
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 module spimaster (clk, cs, spiclk, datain, dataoutpin); input clk, datain; output cs, spiclk, doutp; reg spireg; reg [9:0] tick; reg [4:0] count; reg [4:0] moso; reg [9:0] mosi; reg [9:0] data; reg [0:0] dout; ////////////////////////////////////////////////////////// clk /////////// initial begin moso [4:0] = 24; end always@ (negedge clk) //generate spi clk begin tick <= tick + 1; if (tick == 0) spireg = ~spireg; end always@ (negedge spireg) // track number of clock cycles begin count = count + 1; end always@ (negedge clk) if (count == 7) dout = 1; else if (count == 8) dout = 1; else dout = 0; assign dataout = dout; assign cs = !(count <= 25); assign spiclk = spireg; endmodule
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